Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors

Bellas, Nikolaos

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https://hdl.handle.net/2142/103935 Copy

Description

Title

Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors

Author(s)

Bellas, Nikolaos

Issue Date

1998

Keyword(s)

• Low power design
• Memory hierarchy
• Compiler optimizations
• Cache memories

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign.

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-98-2226, DAC-70

Type of Resource

text

Language

en

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http://hdl.handle.net/2142/103935

Sponsor(s)/Grant Number(s)

INTEL

Owning Collections