Totally Self-checking Circuits and Testable CMOS Circuits

Jha, Niraj Kumar

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https://hdl.handle.net/2142/103907 Copy

Description

Title

Totally Self-checking Circuits and Testable CMOS Circuits

Author(s)

Jha, Niraj Kumar

Issue Date

1986-06

Keyword(s)

• Concurrent error detection
• CMOS
• Domino-CMOS
• Design
• Encoding
• Fault models
• Self-checking circuits
• Testability
• nMOS

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-86-2217, CSG-51

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/103907

Sponsor(s)/Grant Number(s)

• Office of Naval Research / N00039-80-C-0556
• Semiconductor Research Corporation / SRC RSCH 84-06-049

Owning Collections