Study of Voltage and Process Variations Impact on the Path Delays of Arithmetic Units

Kong, Chhay Tep

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https://hdl.handle.net/2142/103897 Copy

Description

Title

Study of Voltage and Process Variations Impact on the Path Delays of Arithmetic Units

Author(s)

Kong, Chhay Tep

Issue Date

2008-11

Keyword(s)

• Voltage overscaling
• Process variations
• VOS error model
• Arithmetic units
• Adder architecture
• Multiplier
• MAC
• FIR filter
• error resilient DSP system

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-08-2220, DAC-112

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/103897

Sponsor(s)/Grant Number(s)

GSRC

Owning Collections