VLSI Architectures for Iterative Channel Decoders

Mansour, Mohammad Monzer

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https://hdl.handle.net/2142/103855 Copy

Description

Title

VLSI Architectures for Iterative Channel Decoders

Author(s)

Mansour, Mohammad Monzer

Issue Date

2003-10

Keyword(s)

• Turbo
• LDPC
• Complexity
• High-throughput
• Low-power

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-03-2221, DAC-101

Type of Resource

text

Language

en

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http://hdl.handle.net/2142/103855

Sponsor(s)/Grant Number(s)

National Science Foundation / NSF CCR 00-00987

Owning Collections