Enhancing Defect Coverage of VLSI Chips by Using Cost Effective Delay Fault Tests

Sharma, Manish

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https://hdl.handle.net/2142/103854 Copy

Description

Title

Enhancing Defect Coverage of VLSI Chips by Using Cost Effective Delay Fault Tests

Author(s)

Sharma, Manish

Issue Date

2003-10

Keyword(s)

• VLSI testing
• Delay fault testing
• Path delay test generation
• Design for test

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-03-2220, CRHC-03-11

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/103854

Sponsor(s)/Grant Number(s)

• Semiconductor Research Corp. / SRC 99-TJ-717
• DARPA
• Hewlett Packard

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