Layout Generation for Deep Submicron CMOS Circuits

Mansour, Makram Monzer

Permalink

https://hdl.handle.net/2142/103813 Copy

Description

Title

Layout Generation for Deep Submicron CMOS Circuits

Author(s)

Mansour, Makram Monzer

Issue Date

2002-10

Keyword(s)

• Systolic architecture
• Detay models
• Pcell
• Parameterized cell
• Automtic layout generation

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-02-2215, DAC-86

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/103813

Sponsor(s)/Grant Number(s)

DARPA

Owning Collections