University of Illinois Urbana-Champaign

A High Level Approach to Test Generation for VLSI Circuits

Narain, Prakash

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https://hdl.handle.net/2142/103666

Description

Title
A High Level Approach to Test Generation for VLSI Circuits
Author(s)
Narain, Prakash
Issue Date
1992-03
Keyword(s)
  • Test generation
  • VLSI circuits
  • Gate level
  • Circuit model
  • Algorithm
Publisher
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report Name or Number
Coordinated Science Laboratory Report no. CRHC-92-07
Type of Resource
text
Language
en
Permalink
http://hdl.handle.net/2142/103666
Sponsor(s)/Grant Number(s)
  • General Electric
  • Semiconductor Research Corp.

Owning Collections

Report - Coordinated Science Laboratory PRIMARY