University of Illinois Urbana-Champaign

Timing Analysis of Digital VLSI Circuits with Emphasis on Interconnect Modeling, Delay, and Crosstalk

Thong, Sidney

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https://hdl.handle.net/2142/103631

Description

Title
Timing Analysis of Digital VLSI Circuits with Emphasis on Interconnect Modeling, Delay, and Crosstalk
Author(s)
Thong, Sidney
Issue Date
2000-05
Keyword(s)
  • Interconnect
  • Crosstalk
  • VLSI circuits
  • Timing delay
  • Coupling
Publisher
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report Name or Number
Coordinated Science Laboratory Report no. UILU-ENG-00-2204, DAC-78
Type of Resource
text
Language
en
Permalink
http://hdl.handle.net/2142/103631
Sponsor(s)/Grant Number(s)
University of Illinois

Owning Collections

Report - Coordinated Science Laboratory PRIMARY