MNA stamping for transient circuit simulation using SPICE
Verma, Vishesh
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https://hdl.handle.net/2142/102467
Description
Title
MNA stamping for transient circuit simulation using SPICE
Author(s)
Verma, Vishesh
Issue Date
2018-12-03
Director of Research (if dissertation) or Advisor (if thesis)
Schutt-Ainé, José E.
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
MNA
Stamping
SPICE
simulation
Abstract
Simulation is an essential step in the circuit design procedure, helping to verify the behavior of a designed circuit and dramatically reducing the time and effort required for debugging a given design. However, to analyze this behavior, we require an interface between the circuit design and the computer’s computational capabilities. This translation can be done in various ways depending on what aspect of the circuit is desired to be modeled (steady-state, transient, etc.). In this thesis, we explore two of these (steady-state MNA formulation and State-Space formulation) as a first step towards transient analysis.
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