An on-chip three-level boost converter for energy harvesting application
Ng, Pei Han
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https://hdl.handle.net/2142/101831
Description
Title
An on-chip three-level boost converter for energy harvesting application
Author(s)
Ng, Pei Han
Issue Date
2018-07-19
Director of Research (if dissertation) or Advisor (if thesis)
Pilawa-Podgurski, Robert
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Date of Ingest
2018-09-27T16:47:36Z
Keyword(s)
three-level boost converter
hybrid
switched capacitor (SC)
current mode control
delay-equalized
level shifter
capacitor balancing
Abstract
The first on-chip three-level boost converter with 0.28 mm2 die size is implemented using 65 nm CMOS technology. Leveraging the advantages of hybrid switched capacitor converters, the converter manages to provide a maximum output voltage of 4.5 V with the available 2.5 V devices in this technology. The issue of capacitor imbalance, which has always been one of the factors that hinder high-efficiency power converters, is resolved by the hybrid current mode controller proposed in this work. The hardware implementation demonstrates that the capacitor converges to its balance voltage within 270 μs. A new level shifter circuitry is established in this thesis to mitigate the effect of asymmetrical gate signals by the level shifter. This delay-equalized level shifter is able to produce a symmetric delay less than 1 ns, allowing high-frequency phase-shifted switching operation in a hybrid switched capacitor (SC) converter. Together with both output voltage regulation and capacitor balancing, the converter operates efficiently up to 45 MHz for wide input range from 0.5 V to 3.0 V. This converter achieves a peak efficiency of 97.5% and peak output current of 83 mA.
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