Failures caused by supply fluctuations during system-level ESD

Xiu, Yang

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https://hdl.handle.net/2142/100889 Copy

Description

Title

Failures caused by supply fluctuations during system-level ESD

Author(s)

Xiu, Yang

Issue Date

2018-01-04

Director of Research (if dissertation) or Advisor (if thesis)

Rosenbaum, Elyse

Doctoral Committee Chair(s)

Rosenbaum, Elyse

Committee Member(s)

• Schutt-Ainé, José E.
• Hanumolu, Pavan Kumar
• Gong, Songbin

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Date of Ingest

2018-09-04T20:26:29Z

Keyword(s)

• System-level ESD
• supply noise
• IEC 61000-4-2

Abstract

It is necessary to design robust electronic systems against system-level electrostatic discharge (ESD). In additional to withstanding ESD without hard failures (permanent damage), it is important that the system is robust against soft failures (recoverable loss of function or data), which can be caused by ESD-induced noise on signal inputs and power nets. Besides radiation, the current injection into the circuit alone can cause these disturbances, especially the sharp current spike of a high amplitude in system-level ESD. The waveform of this current is similar in various ESD test setups. Circuit models with distributed elements enable accurate modeling of the system-level ESD current in contact discharge. Experiments have shown that ESD-induced noise on signal traces starts to disturb the IO input at very low ESD levels, and the effectiveness of the transient voltage suppressor (TVS) on board is limited. The noise on supply is global to integrated circuit (IC), as it travels across all the power domains. The waveform of the noise depends on the polarity of the ESD current and the type of ESD protection. The experiments have shown that the supply fluctuation can be quite severe, as a strong reverse of the on-chip supply is indicated by monitor circuits starting from the ESD levels below the common required passing level. This poses a requirement of a minimum amount of on-chip decoupling capacitances (decaps) to limit the amplitude of supply fluctuations. This requirement is similar whether the supply voltage is generated on-chip or off-chip, as long as a large amount of off-chip decap is used and connected to the board ground. If the supply voltage is generated on-chip, the regulator needs to be carefully designed against ESD induced noise. In addition, the rail clamp, if not optimized, deteriorates the power integrity with its instability. The ESD-induced supply fluctuation may cause latch-up without careful attention to the well-bias scheme.

Graduation Semester

2018-05

Type of Resource

text

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http://hdl.handle.net/2142/100889

Copyright and License Information

Copyright 2018 Yang Xiu

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