Director of Research (if dissertation) or Advisor (if thesis)
Chen, Deming
Department of Study
Electrical & Computer Eng
Discipline
Electrical and Computer Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Field programmable gate array (FPGA)
High-level synthesis (HLS)
Compute unified device architecture (CUDA)
Abstract
The demand for high-performance computing has been growing significantly in the past decade. The bottleneck of Moore's law and the increasing power consumption in the traditional computing industry have stimulated the popularity of parallel computing. GPUs and FPGAs became popular and played very important roles in heterogeneous systems for accelerating various compute intensive tasks in different areas. Modern GPUs can execute more than thousands of threads, providing strong parallelism. FPGAs, however, provide highly customized concurrency for parallel kernels. The current version of source-to-source compiler FCUDA, which transforms CUDA kernel code into synthesizable C code, exploits the parallelism in different applications with the help of the manually inserted pragmas by the programmers. The additional effort to tweak the code to enable efficient mapping of the tasks across the heterogeneous architectures cannot be ignored. In this thesis, a new code optimization flow is proposed. The flow will restructure and analyze the CUDA kernel code, optimizing the performance by extracting the parallelism in GPU devices. The generated C code will further be synthesized and programmed on FPGAs. With help of the new flow, there is no need for programmers to manually annotate and tweak the source code, making the whole process a push-button one.
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