Verify CMOS inverter circuit model using thin variable technique
Meng, Yu
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https://hdl.handle.net/2142/97871
Description
Title
Verify CMOS inverter circuit model using thin variable technique
Author(s)
Meng, Yu
Contributor(s)
Mitra, Sayan
Issue Date
2017-05
Keyword(s)
CMOS inverter circuit model
input verification of nonlinear and hybrid circuit models
metastability of circuits
Abstract
There has been progress in verification of nonlinear and hybrid systems
in the recent years using algorithms that combine simulation data with
model-based sensitivity analysis. These approaches only handle closed
models, that is, models without inputs. The naïve introduction of models
of input signals breaks these approaches, as typical inputs (fast sigmoids,
discontinuous functions) for analog and mixed analog-signal circuits
make the system highly sensitive and the number of needed simulations
grow rapidly. In this thesis, we present a new technique for verifying
nonlinear and hybrid circuit models with inputs. A key result in
the thesis shows that once an input signal is fixed, the sensitivity analysis
of the model can be performed much more precisely. Based on this
observation, we extend a discrepancy-based verification algorithm and
apply it to a suite of nonlinear and hybrid models of CMOS digital circuits
under different input signals. The models are low-dimensional but
involve highly nonlinear ODEs, with nearly hundreds of logarithmic and
exponential terms, and therefore, have challenged existing verification approaches
and tools. Our implementation of the new algorithm is able to
verify these models; some of our experiments analyze the metastability of
bistable circuits, which involve very sensitive ODEs. Our results not only
demonstrate the feasibility of our approach, but also provided interesting
insights like the close connection between metastability recovery time and
sensitivity.
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