Design and Simulation of a Charge-Pump Phase-Locked Loop in 65 nm CMOS Technology
Rajwardan, Ashwarya
This item is only available for download by members of the University of Illinois community. Students, faculty, and staff at the U of I may log in with your NetID and password to view the item. If you are trying to access an Illinois-restricted dissertation or thesis, you can request a copy through your library's Inter-Library Loan office or purchase a copy directly from ProQuest.
Permalink
https://hdl.handle.net/2142/97837
Description
Title
Design and Simulation of a Charge-Pump Phase-Locked Loop in 65 nm CMOS Technology
Author(s)
Rajwardan, Ashwarya
Contributor(s)
Schutt-Ainé, José
Issue Date
2016-12
Keyword(s)
PLL
VCO
Charge Pump
Phase and Frequency Detector
PFD
TSPC
Divide Counter
Abstract
This thesis gives a brief overview of a basic PLL circuit and reports the in-depth analysis of the design procedure and working of a charge-pump phase-locked loop (PLL) in 65 nm CMOS technology. The design is done for a target output frequency of 1.2 GHz and the goal is to use it in a transmitter block of a high-speed serial link (HSSL). A thorough discussion of simulation results with phase noise and jitter results using circuit simulation tool follows the analysis.
Use this login method if you
don't
have an
@illinois.edu
email address.
(Oops, I do have one)
IDEALS migrated to a new platform on June 23, 2022. If you created
your account prior to this date, you will have to reset your password
using the forgot-password link below.