Logic and Fault Simulation of VLSI Circuits Including Hierarchical Techniques
Saab, Daniel Georges
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https://hdl.handle.net/2142/88612
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Title Logic and Fault Simulation of VLSI Circuits Including Hierarchical Techniques Author(s) Saab, Daniel Georges Issue Date 1988-01 Keyword(s) Logic simulation Fault simulation Switch-level models Hierarchical techniques VLSI circuits Parallel-concurrent fault simulation MOS circuits Bipolar circuits Date of Ingest 2015-12-10T23:22:02Z 2017-07-15T01:46:25Z Publisher Coordinated Science Laboratory, University of Illinois at Urbana-Champaign Series/Report Name or Number Coordinated Science Laboratory Report no. UILU-ENG-88-2208, DAC-10 Type of Resource text Genre of Resource Report (Grant or Annual) Language en Permalink http://hdl.handle.net/2142/88612 Sponsor(s)/Grant Number(s) Semiconductor Research Corporation / SRC 86-12-109 TRW Corporation
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