Efficient Direct-Method Parallel Circuit Simulation Using Multilevel Node Tearing

Chang, Mi-Chang

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https://hdl.handle.net/2142/88614 Copy

Description

Title

Efficient Direct-Method Parallel Circuit Simulation Using Multilevel Node Tearing

Author(s)

Chang, Mi-Chang

Issue Date

1989-01

Keyword(s)

• Circuit simulation
• Parallel processing
• Multilevel partitioning
• Direct parallel solution
• Sparse matrices
• Scheduling
• VLSI circuits

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-89-2201, DAC-13

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/88614

Sponsor(s)/Grant Number(s)

Texas Instruments, Inc.

Owning Collections