Parallel Processing for VLSI Simulation

Mueller-Thuns, Robert Bernard

Permalink

https://hdl.handle.net/2142/88634 Copy

Description

Title

Parallel Processing for VLSI Simulation

Author(s)

Mueller-Thuns, Robert Bernard

Issue Date

1990-08

Keyword(s)

• Gate-level logic
• Fault simulation
• Preprocessing
• Synchronization
• Switch-level simulation
• Parallel framework

Publisher

Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-90-2230, CRHC-90-2

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/88634

Sponsor(s)/Grant Number(s)

• Semiconductor Research Corporation
• Motorola, Inc.

Owning Collections