Timing Verification and Synthesis of Circuits for Delay Fault Testability

Roy, Kaushik

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https://hdl.handle.net/2142/88640 Copy

Description

Title

Timing Verification and Synthesis of Circuits for Delay Fault Testability

Author(s)

Roy, Kaushik

Issue Date

1990-09

Keyword(s)

• Testability
• RTL
• Transfer
• Robust
• Combinational logic circuit

Publisher

Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-90-2244, CRHC-90-11

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/88640

Sponsor(s)/Grant Number(s)

• Semiconductor Research Corporation / 89-DP-109
• Texas Instruments

Owning Collections