University of Illinois Urbana-Champaign

Algorithms for Minimizing Test Sets for CMOS VLSI Circuits

Stancil, Charles Jay

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https://hdl.handle.net/2142/75309

Description

Title
Algorithms for Minimizing Test Sets for CMOS VLSI Circuits
Author(s)
Stancil, Charles Jay
Issue Date
1985-05
Keyword(s)
  • CMOS
  • Stuck-open faults
  • Testing
  • Built-in self-test
  • Minimization
Publisher
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report Name or Number
Coordinated Science Laboratory Report no. CSG-42
Type of Resource
text
Language
English
Permalink
http://hdl.handle.net/2142/75309
Sponsor(s)/Grant Number(s)
Semiconductor Research Corporation / SRC RSCH 84-06-049

Owning Collections

Report - Coordinated Science Laboratory PRIMARY