Register Transfer Level Design-for-Testability Methodology for a Frozen Clock Testing Strategy
Slutter, Andrew Bryan
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https://hdl.handle.net/2142/75467
Description
Title
Register Transfer Level Design-for-Testability Methodology for a Frozen Clock Testing Strategy
Author(s)
Slutter, Andrew Bryan
Issue Date
2001-08
Keyword(s)
Design for testability
Frozen clock testing strategy
Register transfer level
Sequential circuit testing
Publisher
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
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