iSITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI Circuits

Gee, Perry

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https://hdl.handle.net/2142/88616 Copy

Description

Title

iSITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI Circuits

Author(s)

Gee, Perry

Issue Date

1989-12

Keyword(s)

• Synthesis
• Cell generation
• Physical layout
• Symbolic layout
• Metal-metal matrix
• Logic design compaction
• Delay optimization

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-89-2243, DAC-16

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/88616

Sponsor(s)/Grant Number(s)

• Joint Services Electronics Program / N00014-84-C-0149
• Semiconductor Research Corporation / SRC 88-DP-109
• Texas Instruments

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