University of Illinois Urbana-Champaign

The Design of a VLSI Systolic Array Processor Cell with Concurrent Error Detection

Chin, Michael Tsung Sheng

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https://hdl.handle.net/2142/75283

Description

Title
The Design of a VLSI Systolic Array Processor Cell with Concurrent Error Detection
Author(s)
Chin, Michael Tsung Sheng
Issue Date
1982-10
Keyword(s)
  • VLSI design
  • Systolic
  • Array processor
  • Concurrent error detection
  • RESO
  • Booth's recoding scheme
  • Prefix carry computation
Publisher
Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report Name or Number
Coordinated Science Laboratory Report no. CSG-11
Type of Resource
text
Language
English
Permalink
http://hdl.handle.net/2142/75283
Sponsor(s)/Grant Number(s)
Naval Electronics Systems Command VHSIC Program / N00039-80-C-0556

Owning Collections

Report - Coordinated Science Laboratory PRIMARY