University of Illinois Urbana-Champaign

A Parallel VLSI Architecture for Sparse Matrix Computation

Hsu, Peter Yan-Tek

This item is only available for download by members of the University of Illinois community. Students, faculty, and staff at the U of I may log in with your NetID and password to view the item. If you are trying to access an Illinois-restricted dissertation or thesis, you can request a copy through your library's Inter-Library Loan office or purchase a copy directly from ProQuest.

Permalink

https://hdl.handle.net/2142/75329

Description

Title
A Parallel VLSI Architecture for Sparse Matrix Computation
Author(s)
Hsu, Peter Yan-Tek
Issue Date
1982-07
Keyword(s)
  • Physical system simulation
  • Sparse matrix
  • VLSI architecture
  • Parallel processing
  • Array processor
  • Resource scheduling
  • Synchronization
Publisher
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report Name or Number
Coordinated Science Laboratory Report no. CSG-8
Type of Resource
text
Language
English
Permalink
http://hdl.handle.net/2142/75329
Sponsor(s)/Grant Number(s)
Naval Electronics Systems Command VHSIC Program / N00039-80-C-0556

Owning Collections

Report - Coordinated Science Laboratory PRIMARY