University of Illinois Urbana-Champaign

Test Time and Test Data Volume Reduction Techniques for VLSI Circuits

Pandey, Amit Raj

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https://hdl.handle.net/2142/75466

Description

Title
Test Time and Test Data Volume Reduction Techniques for VLSI Circuits
Author(s)
Pandey, Amit Raj
Issue Date
2001-06
Keyword(s)
  • Test application time
  • Test data volume
  • Design for testability
  • Built-in self test
  • System-on-chip
Publisher
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report Name or Number
Coordinated Science Laboratory Report no. UILU-ENG-01-2217, CRHC-01-06
Type of Resource
text
Language
English
Permalink
http://hdl.handle.net/2142/75466
Sponsor(s)/Grant Number(s)
Semiconductor Research Corporation / SRC 99-TJ-717

Owning Collections

Report - Coordinated Science Laboratory PRIMARY