University of Illinois Urbana-Champaign

High-Level Methodologies for Test Generation and Logic Simulation

Dave, Utpal Jagdish

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https://hdl.handle.net/2142/75285

Description

Title
High-Level Methodologies for Test Generation and Logic Simulation
Author(s)
Dave, Utpal Jagdish
Issue Date
1989-11
Keyword(s)
  • Test generation
  • Logic simulation
  • High-level representations
  • VLSI
Publisher
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report Name or Number
Coordinated Science Laboratory Report no. UILU-ENG-89-2238, CSG-114
Type of Resource
text
Language
English
Permalink
http://hdl.handle.net/2142/75285
Sponsor(s)/Grant Number(s)
Semiconductor Research Corporation / 88-DP-109

Owning Collections

Report - Coordinated Science Laboratory PRIMARY