Efficient Equivalence Checking in a Modular Design Environment

Hasteer, Gagan

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https://hdl.handle.net/2142/88508 Copy

Description

Title

Efficient Equivalence Checking in a Modular Design Environment

Author(s)

Hasteer, Gagan

Issue Date

1997-12

Keyword(s)

• Equivalence checking
• Modular design
• Steady states
• Sequential hardware equivalence
• Interface verification
• Safety property
• Multi-phase design methodology
• Minimum area retiming

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-97-2234, CRHC-97-19

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/88508

Sponsor(s)/Grant Number(s)

DARPA / DAAH04-94-G-0273

Owning Collections