New Techniques to Verify Timing Correctness of Integrated Circuits

Heragu, Keerthinarayan Prasanna

Permalink

https://hdl.handle.net/2142/88507 Copy

Description

Title

New Techniques to Verify Timing Correctness of Integrated Circuits

Author(s)

Heragu, Keerthinarayan Prasanna

Issue Date

1997-12

Keyword(s)

• Delay fault testing
• Timing analysis
• Fault model
• Test generation

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-97-2233, CRHC-97-18

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/88507

Sponsor(s)/Grant Number(s)

• Semiconductor Research Corp. and DARPA; 96-DP-109 and DABT63-95-C-0069
• Hewlett-Packard

Owning Collections