University of Illinois Urbana-Champaign

Symbolic Switch-Level Logic and Fault Simulation of MOS VLSI Circuits

Saab, Daniel Georges

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https://hdl.handle.net/2142/75217

Description

Title
Symbolic Switch-Level Logic and Fault Simulation of MOS VLSI Circuits
Author(s)
Saab, Daniel Georges
Issue Date
1985-09
Keyword(s)
  • Logic simulation
  • Fault simulation
  • Switch-level logic simulation
  • VLSI circuits
  • Symbolic logic expressions
  • Concurrent fault simulation
Publisher
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report Name or Number
Coordinated Science Laboratory Report no. UILU-ENG-85-2231
Type of Resource
text
Language
English
Permalink
http://hdl.handle.net/2142/75217
Sponsor(s)/Grant Number(s)
Semiconductor Research Corporation / SRC-RSCH-84-06-049

Owning Collections

Report - Coordinated Science Laboratory PRIMARY