Hierarchical Approaches to VLSI Circuit Layout

Sarrafzadeh, Majid

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https://hdl.handle.net/2142/75712 Copy

Description

Title

Hierarchical Approaches to VLSI Circuit Layout

Author(s)

Sarrafzadeh, Majid

Issue Date

1986-12

Keyword(s)

• Top-down approach
• Bottom-up approach
• Channel Routing Problem
• 45° grid
• LLSI circuit layout

Publisher

Applied Computation Theory, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-86-2240, ACT-72

Type of Resource

text

Language

English

Permalink

http://hdl.handle.net/2142/75712

Sponsor(s)/Grant Number(s)

Semiconductor Research Corporation / SRC-RSCH-84-06-049-6

Owning Collections