Techniques to Speedup Test Generation for VLSI Circuits

Chandra, Susheel Jagdish

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https://hdl.handle.net/2142/88609 Copy

Description

Title

Techniques to Speedup Test Generation for VLSI Circuits

Author(s)

Chandra, Susheel Jagdish

Issue Date

1989-09

Keyword(s)

• Test generation
• Logic circuits
• Parallel processing
• Mapping strategies

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-89-2232, CSG-109

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/88609

Sponsor(s)/Grant Number(s)

Semiconductor Research Corporation / 88-DP-109

Owning Collections