University of Illinois Urbana-Champaign

A Switch-Level Concurrent Fault Simulator for MOS Circuits

Lee, Terry Ping-Chung

This item is only available for download by members of the University of Illinois community. Students, faculty, and staff at the U of I may log in with your NetID and password to view the item. If you are trying to access an Illinois-restricted dissertation or thesis, you can request a copy through your library's Inter-Library Loan office or purchase a copy directly from ProQuest.

Permalink

https://hdl.handle.net/2142/75367

Description

Title
A Switch-Level Concurrent Fault Simulator for MOS Circuits
Author(s)
Lee, Terry Ping-Chung
Issue Date
1991-01
Keyword(s)
  • Switch-level simulation
  • MOS VLSI circuits
  • Concurrent fault simulation
  • Transistor level faults
  • Switch-level matrix algebra
  • Fault models
Publisher
Analog and Digital Circuits, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report Name or Number
Coordinated Science Laboratory Report no. UILU-ENG-91-2201, DAC-26
Type of Resource
text
Language
English
Permalink
http://hdl.handle.net/2142/75367
Sponsor(s)/Grant Number(s)
Semiconductor Research Corporation / SRC 88-DP-109

Owning Collections

Report - Coordinated Science Laboratory PRIMARY