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Reliability Models for Double Chipkill Detect/Correct Memory Systems
Jian, Xun; Blanchard, Sean; Debardeleben, Nathan; Sridharan, Vilas; Kumar, Rakesh
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https://hdl.handle.net/2142/90435
Description
- Title
- Reliability Models for Double Chipkill Detect/Correct Memory Systems
- Author(s)
- Jian, Xun
- Blanchard, Sean
- Debardeleben, Nathan
- Sridharan, Vilas
- Kumar, Rakesh
- Issue Date
- 2013-03
- Keyword(s)
- ECC
- Memory
- Chipkill correct
- Modeling
- Reliability
- Date of Ingest
- 2016-07-07T13:59:39Z
- 2017-07-14T23:14:59Z
- Abstract
- Chipkill correct is an advanced type of error correction used in memory subsystems. Existing analytical approaches for modeling the reliability of memory subsystems with chipkill correct are limited to those with chipkill correct solutions that can only guarantee correction of errors in a single DRAM device. However, chipkill correct solutions capable of guaranteeing the detection and even correction of errors in up to two DRAM devices have become common in existing HPC systems. Analytical reliability models are needed for such memory subsystems. This paper proposes analytical models for the reliability of double chipkill detect and/or correct. Validation against Monte Carlo simulations shows that the outputs of our analytical models are within 3.9% of Monte Carlo simulations, on average.
- Publisher
- Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
- Series/Report Name or Number
- Coordinated Science Laboratory Report no. UILU-ENG-13-2202, CRHC-13-02
- Type of Resource
- text
- Genre of Resource
- Technical Report
- Language
- en
- Permalink
- http://hdl.handle.net/2142/90435
- Sponsor(s)/Grant Number(s)
- Department of Energy /DE-FC02-06ER25750
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