A Minimum Area VLSI Architecture for O(logn) Time Sorting

Bilardi, G.; Preparata, F.P.

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https://hdl.handle.net/2142/74207 Copy

Description

Title

A Minimum Area VLSI Architecture for O(logn) Time Sorting

Author(s)

• Bilardi, G.
• Preparata, F.P.

Issue Date

1983-11

Keyword(s)

• VLSI complexity
• Area-time trade-off
• Combination sorting
• Bitonic merging
• Cube-connected-cycles
• Mesh
• Orthogonal trees
• Optimal algorithms
• Parallel computation

Publisher

Applied Computation Theory Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG 83-2227, R-1006, ACT-45

Type of Resource

text

Language

English

Permalink

http://hdl.handle.net/2142/74207

Sponsor(s)/Grant Number(s)

• Joint Services Electronics Program / N00014-79-C-0424
• IBM predoctoral Fellowship

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