IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors
Chang, Pohua P.; Mahlke, Scott A.; Chen, William Y.; Warter, Nancy J.; Hwu, Wen-Mei W.
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https://hdl.handle.net/2142/74523
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Title IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors Author(s) Chang, Pohua P. Mahlke, Scott A. Chen, William Y. Warter, Nancy J. Hwu, Wen-Mei W. Issue Date 1991-02 Keyword(s) Multiple-instruction issue processors Optimizing Compiler code Scheduling code Transformation concurrency Publisher Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign Series/Report Name or Number Coordinated Science Laboratory Report no. UILU-ENG-91-2208, CRHC-91-4 Type of Resource text Language English Permalink http://hdl.handle.net/2142/74523 Sponsor(s)/Grant Number(s) National Aeronautics and Space Administration / NASA NAG 1-613 National Science Foundation (NSF) / MIP-8809478 NCR Office of Naval Research / N00014-88-K-0656
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