University of Illinois Urbana-Champaign

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Showing 121–150 of 1,930 items
Thumbnail for Parallel Processing Techniques for the Simulation of MOS VLSI Circuits Using Waveform Relaxation
Parallel Processing Techniques for the Simulation of MOS VLSI Circuits Using Waveform Relaxation
Smart, David William

Thumbnail for The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
Rogers, William Arthur

Thumbnail for Statistical Design of MOS VLSI Circuits with Designed Experiments
Statistical Design of MOS VLSI Circuits with Designed Experiments
Yu, Tat-Kwan Edgar

Thumbnail for Delay Fault Testing for Enhanced Full Scan Based Circuits
Delay Fault Testing for Enhanced Full Scan Based Circuits
Sharma, Manish

Thumbnail for Worst Case Voltage Drops in Power and Ground Buses of CMOS VLSI Circuits
Worst Case Voltage Drops in Power and Ground Buses of CMOS VLSI Circuits
Kriplani, Harish

Thumbnail for Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers
Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers
Tejayadi, Ongky

Thumbnail for Design, Analysis and Reconfiguration of Defect-Tolerant VLSI and Parallel Processor Arrays
Design, Analysis and Reconfiguration of Defect-Tolerant VLSI and Parallel Processor Arrays
Shi, Weiping

Thumbnail for iSITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI Circuits
iSITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI Circuits
Gee, Perry

Thumbnail for Parallel Algorithms for Sequential Circuit Fault Simulation and Test Generation
Parallel Algorithms for Sequential Circuit Fault Simulation and Test Generation
Krishnaswamy, Dilip

Thumbnail for Evaluation of a Design for Concurrent Error Detection and Testability in Large Storage/Logic Arrays
Evaluation of a Design for Concurrent Error Detection and Testability in Large Storage/Logic Arrays
Maciukenas, Thomas Brian

Thumbnail for Parallel Algorithms for Test Generation and Fault Simulation
Parallel Algorithms for Test Generation and Fault Simulation
Patil, Srinivas

Thumbnail for A Convex Programming Approach to Problems in VLSI Design
A Convex Programming Approach to Problems in VLSI Design
Sapatnekar, Sachin Suresh

Thumbnail for Parallel Processing for VLSI Simulation
Parallel Processing for VLSI Simulation
Mueller-Thuns, Robert Bernard

Thumbnail for Fast and Accurate CMOS Bridging Fault Simulation
Fast and Accurate CMOS Bridging Fault Simulation
Rearick, Jeffrey R.

Thumbnail for Back in the chips
Back in the chips
Bridges, Kenneth

Thumbnail for Time-based strategies for semiconductor manufacture and test
Time-based strategies for semiconductor manufacture and test
Levitt, Marc Elliot

Thumbnail for Tunneling in Semiconductors
Tunneling in Semiconductors
Duke, C.B.

Thumbnail for The u.s. Computer Industry: An Economic-Legal Analysis of Its Major Growth Factors
The u.s. Computer Industry: An Economic-Legal Analysis of Its Major Growth Factors
Soma, John Trygve

Thumbnail for Essays on Intellectual Property Protection and Innovation in Agriculture
Essays on Intellectual Property Protection and Innovation in Agriculture
Umeno, Soyoko

Thumbnail for Behavioral analysis of insulated gate bipolar transistors during hard and soft turn-off
Behavioral analysis of insulated gate bipolar transistors during hard and soft turn-off
Banerjee, Abhishek

Thumbnail for Doped Titanium Oxide Photcatalysts: Preparation, Structure and Interaction With Viruses
Doped Titanium Oxide Photcatalysts: Preparation, Structure and Interaction With Viruses
Li, Qi

Thumbnail for The Summary of Engineering Research 2004
The Summary of Engineering Research 2004
University of Illinois at Urbana-Champaign. College of Engineering

Thumbnail for One-Electron and Phonon-Assisted Tunneling in N-Ge Schottky Barriers
One-Electron and Phonon-Assisted Tunneling in N-Ge Schottky Barriers
Davis, L.C.; Steinrisser, F.

Thumbnail for An FPGA Based Testbench for Reliability and Endurance Characterization of Nonvolatile Memory
An FPGA Based Testbench for Reliability and Endurance Characterization of Nonvolatile Memory
Rao, Vikram M.N.

Thumbnail for The Korean economic crisis of the 1990s
The Korean economic crisis of the 1990s
Chen, Andy H.

Thumbnail for Tunneling Spectroscopy in Degenerate p-Type Silicon
Tunneling Spectroscopy in Degenerate p-Type Silicon
Cullen, D.E.; Wolf, E.L.; Compton, W. Dale

Thumbnail for Tunneling Measurement of Electron-Plasmon Interactions in Degenerate Semiconductors
Tunneling Measurement of Electron-Plasmon Interactions in Degenerate Semiconductors
Duke, C.B.; Rice, M.J.; Steinrisser, F.

Thumbnail for Low-power giga-bit per second optoelectronic integrated circuits for two-dimensional smart-pixel arrays
Low-power giga-bit per second optoelectronic integrated circuits for two-dimensional smart-pixel arrays
Chang, Wei-Heng

Thumbnail for The Summary of Engineering Research 2005
The Summary of Engineering Research 2005
University of Illinois at Urbana-Champaign. College of Engineering

Thumbnail for The effect of technological complexity on innovation performance, employee entrepreneurship and mobility: three essays
The effect of technological complexity on innovation performance, employee entrepreneurship and mobility: three essays
Ganco, Martin