Implementation and Analysis of 4×4 SRAM Array

Chan, Muk Yeh

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https://hdl.handle.net/2142/124858 Copy

Description

Title

Implementation and Analysis of 4×4 SRAM Array

Author(s)

Chan, Muk Yeh

Issue Date

2023-05-01

Keyword(s)

6-T SRAM; SRAM array; memory system

Abstract

SRAM is a highly developed technology that is used in many applications, including but not restricted to cache memory, processor, VLSI circuit, and CMOS system-on-chip. It can be said that most electronics today involve a memory system. A computer needs to process a huge amount of data every day, it needs a place to temporarily or permanently store the data. So here comes the design of the memory system. The basis of a powerful computer is also a memory system with high capacity and speed. A memory system is not only a place to store data, but also is involved in the whole instruction processing system. Various types of memory are designed in recent years, such as the normal 6-T and 8-T SRAM. A single SRAM cell could store one bit, and the cells form an array in which each address corresponds to a cell. For example, a 32*32 memory system could store 1024 bits of information. This passage will discuss the implementation and design details of a 4*4 SRAM array using 180nm technology and 6-T SRAM cells, as well as the comparison between different types of SRAMs from the aspects of dynamic power consumption and time delay. With the understanding of a 4*4 SRAM array implementation, it will not be hard to expand that to a much large memory system. For the design and analysis of this SRAM array, the Cadence tool, HSPICE simulation tool, and Python are used.

Type of Resource

text

Language

eng

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